Powerful and reliable mainframe CPUs may incorporate duplicate BPUs which work independently to execute the same instruction or instruction series in parallel such that the results can be compared to insure identity. It has now become feasible to incorporate an entire BPU on a VLSI circuit, a feature which has the advantage of not only occupying less space, but also enjoys the capability to run faster. However, there is a practical limit to the number of conductive leads which can be connected to a VLSI circuit. This problem arises because each of the duplicate BPUs has typically required a double word result bus which, for example in one computer family in which the present application finds application, means the provision of two 80-bit result buses to a cache unit, one coupled to each BPU.
One viable approach to obtaining reliable redundant double word transfer of information from the BPUs to the cache within the conductive lead limitations imposed as a practical matter on VLSI chips is disclosed in copending U.S. patent application Ser. No. 08/065,105 entitled CENTRAL PROCESSING UNIT USING DUAL BASIC PROCESSING UNITS AND COMBINED RESULT BUS, filed May 19, 1993, by Donald C. Boothroyd et al and assigned to the assignee of the present application. In that invention, the desired end was achieved by providing a CPU incorporating duplicate BPUs and two cache units, each cache unit being dedicated to handling half-bytes of information. Each cache unit included bit-by-bit comparison circuitry to validate the half-byte results received from both BPUs in the case of single precision operations, and, in the case of double precision operations, one cache unit employed the same bit-by-bit comparison circuitry to validate, for both cache units, the result parity bits, and hence the half-byte results, received from both BPUs.
However, one of the major challenges that traditional mainframe vendors face as personal computers and workstations become more and more powerful is in differentiating their midrange systems from the rapidly advancing smaller machines. One significant area in which mainframe machines can be made distinguishable from the smaller machines is in the area of fault tolerance. Therefore, it would be highly desirable to preserve a high degree of fault tolerant operation while still achieving the necessary chip pin count reduction. The present invention is directed to this end and to obtaining other desirable results which are a consequence of the implementation of the invention.